In general, an electrostatic discharge protecting (referred to herein as an ESD) circuit has been widely used to prevent overcurrent from being applied to an internal circuit in a semiconductor device. Desired attributes of the ESD circuit are a low trigger voltage, a low holding voltage and a low dynamic resistance. Trigger voltage refers to the voltage level at which the SCR switches from a forward-blocking state to a forward conducting state. The holding voltage (or "snap-back voltage") refers to the momentary voltage drop of the SCR due to avalanche breakdown during SCR conduction.
Shown in FIG. 1 is a semiconductor device having a conventional ESD circuit of an SCR structure for satisfying the above requirements. Referring to FIG. 1, an input/output (I/O) pad is connected to an internal circuit 6 between a power supply Vdd and a ground voltage level Vss. Also, the input/output (I/O) pad is connected to an SCR 8, one terminal of which is connected to the internal circuit 6 and the other terminal of which is connected to the ground voltage level Vss. Typically, the SCR can be connected to either the power supply Vdd or the ground voltage level Vss. Here, the SCR will be illustrated with respect to only the connection to the ground voltage level Vss.
In the conventional ESD circuit, however, there are problems in that the trigger voltage is relatively high as compared with the low holding voltage and the low dynamic resistance. One design to reduce the trigger voltage of the ESD circuit to desired levels is proposed in EDL (Electron Device Letter) IEEE published in 1991 by Polygreen--called the LVTSCR (low voltage trigger SCR).
FIG. 2 is a cross-sectional view showing the LVTSCR structure proposed by Polygreen for reducing a high trigger voltage of the conventional ESD circuit The ESD circuit of the LVTSCR includes P-well and N-well regions 15 and 16 formed by implanting impurity ions into a semiconductor substrate 9 and field oxide layers 7a to 7e to define active and nonactive regions in the P-well and N-well regions 15 and 16. Further, the ESD circuit of the LVTSCR includes impurity regions 10 to 14 formed in the active regions by ion-implantation. The concentration of impurity regions 10 to 14 is higher than that in the well regions 15 and 16.
Impurity regions 13 and 14 in the N-well region 16 are connected to the I/O pad and impurity regions 10 and 11 in the P-well region 15 are connected to the ground voltage level Vss. The impurity region 12 is formed between the field oxide layers 7c and 7d, thereby being in contact with both the P-well region 15 and the N-well region 16.
In the above-mentioned ESD circuit of the LVTSCR structure, a first current path discharging the overcurrent is formed in the positive pulse as follows: p.sup.+ (I/O pad) .fwdarw. n.sup.+ (N-well region) .fwdarw. P-well region .fwdarw. n.sup.+ (Vss). In case of a negative pulse, a second current path discharging the overcurrent is formed as follows: n.sup.+ (N-well region) .fwdarw. P-well region (substrate).
FIG. 3 is an equivalent circuit diagram illustrating the ESD protecting circuit of the LVTSCR structure shown in FIG. 2. Referring to FIG. 3, the conventional ESD protecting circuit of the LVTSCR structure forms a PNPN diode between the I/O pad and the ground voltage level Vss and a PN diode 38 having an anode connected to the ground voltage level Vss and a cathode connected to the I/O pad.
FIG. 4 is an I-V characteristic curve of the conventional ESD protecting circuit of the LVTSCR structure shown in FIG. 2. As can readily be seen in FIG. 4, the trigger voltage, the holding voltage and the dynamic resistance of the LVTSCR are lower than those of the simple SCR structure, thus yielding an improved ESD device.
However, although the LVTSCR structure may improve the trigger voltage of a conventional ESD circuit, there still is an important drawback in that the discharging current paths for protecting the internal semiconductor device circuit are formed in only one direction.